1. Technical Field
The present disclosure is related to semiconductor memory devices. In particular, the disclosure is related to a phase change memory device and a program method thereof.
2. Discussion of Related Art
Electrically erasable and programmable semiconductor devices have been increasingly required without a refresh capability of the data stored therein. Presently, there is a trend to enhance capacitance and integrity of semiconductor devices. A typical example of a non-volatile memory device with large capacitance and high integrity without a refresh of stored data is a NAND flash memory. Even when the power supply is turned off, the NAND flash memories keep stored data. Accordingly, such flash memories are widely utilized in many electronic devices, such as portable terminals, portable computers, and so forth.
As shown in the following table 1, data retention characteristics and the number of program/erase cycles without deterioration are closely related with a reliability of the non-volatile memories having a floating gate structure. Stored charges in the form of electrons are driven from the floating gate by various failure mechanisms, thereby reducing a threshold voltage. In contrast, when a floating gate slowly obtains electrons under the condition that a control gate is maintained at a specific voltage, there is a reciprocal effect. As a result, a threshold voltage is increased. The repetition of program/erase cycles causes stress on an oxide layer of a cell transistor and also causes a failure, such as the deterioration of a tunnel oxide layer thereof. In flash memories, there is a problem of program/erase (PE) endurance because charges are trapped in the tunnel oxide layer during program/erase operations. Trapped charges affect a threshold voltage window of the memory devices and a program/erase time of the next cycle.
TABLE 1Code storageData storagePE cycle10K100KRead cycle10E7100KData cycle10 Year10 Year
Flash memories having a storage region for storing data, hereinafter, referred to as a “data storage region”, and a region for storing a code (hereinafter, referred to as “code storage region”) have been suggested. The data storage region and the code storage region have non-volatile memory cells, and each of the non-volatile memory cells has one of an erase state of data “1” and a program state of data “O”. The threshold voltage distributions corresponding to the erase state and the program state are shown in FIG. 1. The threshold voltage of a memory cell having an erase status is lower than a reference voltage (e.g., 0V), and the threshold voltage of a memory cell having a program state is higher than a reference voltage (e.g., 0V). In NAND flash memories with a so-called string structure, as shown in FIG. 2, a read voltage Vread of 0V is applied to a word line (e.g. WL1) of a selected memory cell, and a read voltage Vread of 5V is applied to a word line (e.g. WL0, WL2˜WLm−1) of non-selected memory cells. Non-volatile memory cells are programmed according to a repetition of program loops, and when program loops are repeated, a program voltage supplied to the word lines is stepwise increased by a predetermined increment. Bias conditions of the above-mentioned read and program operations are applied to the data storage region and the code storage region.
As a read operation is repeated, the threshold voltage distribution of the erase memory cells is varied by a read voltage Vread applied to a non-selected word line. For instance, as shown in FIG. 3, the threshold voltage distribution of the eased memory cells is higher than the read voltage (Vread: 0V) applied to the selected word line after read operations are repeated. This is referred to as a “read disturb”. Such a read disturb causes a read failure. In the event that this read failure happened in the code storage region, it is difficult to certify a code stored in the code storage region.